In the fabrication of integrated circuit chip package modules, the circuitry of the IC chip or chips are connected to a first level IC chip package substrate at a large number of interconnect points. Modem high density IC chips may comprise the need for hundreds or more interconnection points so that a very high density of interconnect points is necessary, given the very small size of IC chips. Formation of the interconnects can be accomplished in a number of different ways, whose advantages and disadvantages are described in detail in co-assigned U.S. Pat. No. 5,334,804 to Love, et al., the disclosure of which is incorporated herein by reference. However, as disclosed in that patent, the preferred way to reliably interconnect a chip to a package substrate with a very high density of interconnects is to form high aspect ratio interconnect posts (i.e., posts whose height is typically equal to 4-8 times their diameter) between the substrate and the IC chip. The interconnect posts can be formed on either the substrate or the chip, and may be formed on top of a base pedestal layer. Typically, the diameter of a state-of-the-art high-aspect-ratio interconnect post is on the order of a dozen microns. Such posts can be formed by processes like those described in the aforementioned U.S. Pat. No. 5,334,804.
One reason for using post interconnect is that the circuitry of the IC chip can generate substantial amounts of heat during operation, thereby expanding the dimensions of the chip and generating shear stresses at the ends of the post where they join to the substrate and chip. The higher the aspect ratio of the post, the more easily the post can flex to follow the expansion of the IC chip, and the less shear stress is imposed on the post ends.
As disclosed in U.S. Pat. No. 5,334,804, the interconnect post may be constructed by first forming a spacer layer on top of the substrate (or IC chip), thereafter forming an aperture in the spacer layer that acts as a mold for the post, thereafter depositing or electroplating conductive material into the aperture to form the post, and thereafter removing the spacer layer. It is convenient to use a photoresist to form the spacer layer as photoresist technology is relatively mature and relatively inexpensive. However, it has been the inventors' experience that currently available photoresists are limited in their ability of defining apertures having aspect ratios above approximately 3:1 (height:diameter), with diameters around 12 .mu.m. It is often observed that the bottom portion of such apertures are narrowed down to less than 6 .mu.m, and often to 3 .mu.m. Although posts formed in apertures with such constrictions are electrically operable, they have a higher probability of fracturing at their bottom ends in response to thermal cycling, and consequently have relatively short lifetimes.
One approach to addressing this problem is to form the high aspect-ratio post by first forming a shorter post in a first spacer layer of photoresist, then forming a second photoresist spacer layer on top of the first spacer layer, and thereafter forming a second short post on top of the first short post. Unfortunately, there is a chance that the top post will be misaligned to the first post, thereby creating a constriction point that is susceptible to fracture. Additionally, separate plating operations would be required, which would entail a risk of poor adhesion. Extra processing steps would be required to prevent such risk and ensure good adhesion. Accordingly, it would be preferable to be able to form the post in a single spacer layer to reduce manufacturing costs and prevent misalignments.